Field of the Disclosure
The present disclosure relates to a semiconductor device and a method for manufacturing the same, and in particular, to an ESD protection device and a method for manufacturing the same.
Background of the Disclosure
Electrostatic discharge (ESD) is a phenomenon that charges are released and transferred between integrated circuit chips and external objects. Due to a large quantity of charges being released in a short time, the ESD energy is much higher than the bearing capacity of the chips, which may cause temporary function failure or even permanent damage to the chips. During the process for manufacturing a chip, a bracelet or an anti-static clothing can be used to reduce the damage of ESD. After the chip is fabricated, it is easily affected by the electrostatic discharge between the chip and the external objects when it is used in various environments. An ESD protection device is provided in the chip to offer an electrostatic discharge path for effectively protecting the chip, so that the reliability and service life of the integrated circuit chip is improved.
In modern electronic products such as smartphones, laptops, tablets and LED displays, ESD protection devices are widely used for providing protection to high-speed data ports such as HDMI, USB, DVI, etc., mounted on printed circuit boards (PCBs). These ESD protection devices are either discrete devices or integrated into the chip. For protecting the high-speed data ports, the ESD protection devices are required to have great protection capability as well as low parasitic capacitance (for example, less than 0.5 pF).
The ESD protection device can be implemented based on various circuit structures. FIG. 1 is a longitudinal cross-sectional structural diagram of an ESD protection device, and FIG. 2 is an equivalent circuit diagram of the ESD protection device shown in FIG. 1. As shown in FIG. 2, the ESD protection device includes a Zener diode (or an avalanche diode) DZ being coupled between a power supply terminal VCC and the ground GND, and further includes a rectification diode D1 and a rectification diode D2 coupled in series between the power supply terminal VCC and the ground GND, and an input/output terminal I/O is led at an intermediate node of the rectification diodes D1 and D2. The input/output terminal I/O is, for example, a terminal of a high-speed data port. Corresponding to FIG. 2, a first doped region 107 and an epitaxial semiconductor layer 103 in FIG. 1 constitute the rectification diode D1 in FIG. 2, a second doped region 108, the epitaxial semiconductor layer 103 and a semiconductor substrate 101 constitute the rectification diode D2 in FIG. 2, and the semiconductor substrate 101 and a semiconductor buried layer 102 constitute the Zener diode (or the avalanche diode) DZ in FIG. 2.
When positive ESD or surge occurs near the input/output terminal I/O, the rectification diode D1 is turned on at forward direction, the Zener diode (or avalanche diode) DZ is under reverse breakdown condition. As shown in FIG. 1, an ESD current at the input/output terminal I/O flows through the rectification diode D1 and the Zener diode (or avalanche diode) DZ to the ground GND. Due to the accumulated effect of the current and parasitic capacitance effect of the epitaxial semiconductor layer 103, most of the ESD current will converge in the semiconductor buried layer 102 directly below the first doped region 107, and thus, when the ESD current becomes large, the semiconductor buried layer 102 directly below the first doped region 107, due to the accumulated effects of the ESD current, may be first punctured and eventually cause the Zener diode (or avalanche diode) DZ to fail. FIG. 3 is a top diagram of the ESD protection device shown in FIG. 1. The dashed region in FIG. 3, represents an effective region 109 of the Zener diode (or avalanche diode) DZ, that is, the portion of the semiconductor buried layer 102 directly below the first doped region 107. The region plays a major role in ESD protection performance and anti-surge performance. However, the parasitic capacitance of the ESD protection device is relevant to the area of the first doped region 107, that means, an increase of the area of the doped region 107 will lead to an increase of the parasitic capacitance of the ESD protection device.
Therefore, it is desired that the ESD protection performance and maximum current bearing capacity can be improved without increasing the area of the first doped region.